Micron outlines DRAM and NAND roadmap, including 3D memory and AI-focused designs

Micron has outlined plans to advance its DRAM and 3D NAND technologies, while developing more memory products tailored to customer-specific AI processors and workloads. The roadmap includes wafer bonding, new materials, High-NA EUV lithography and vertically integrated memory designs.

The company’s next-generation 1δ DRAM process is in the yield-ramp stage and is scheduled to enter mass production in the second half of 2027. Micron expects it to deliver a mid-20% increase in bit density over its current 1γ node. The process is planned for use in products including DDR, LPDDR, graphics memory, HBM5, vertical HBM and vertical Edge Inference Memory.

Micron has abandoned plans to make DRAM using 4F² memory cells, saying it does not see a viable scaling path beyond its current position. Its disclosed planar roadmap instead continues with 6F² cells. Later generations are in development, including 1ε, which is expected to use wafer bonding, and ζÅ, which will introduce High-NA EUV lithography. The company has not announced production schedules for those nodes.

Micron is also developing two generations of 3D DRAM, named 3D1 and 3D2. Unlike planar memory, which increases density mainly by shrinking cells, 3D DRAM would add memory cells vertically. Micron says it plans to introduce the technology when its manufacturing cost and performance can compete with conventional DRAM, but has not disclosed architectural details or target dates.

For NAND, Micron plans to move from its current G9 technology to G11, which is expected to increase the number of active layers from 276 to more than 400. G11 will use wafer-on-wafer bonding, and Micron expects it to double bit density compared with G9, increase I/O speed by 50% and reduce energy use per transferred bit by more than 25%. Mass production is scheduled to begin in the second half of 2027.

Beyond G11, Micron is investigating new materials, denser cell designs and more efficient circuitry and data paths. It has not yet identified the materials or provided performance and density targets for later NAND generations.

The company is also working on two NAND architectures for AI applications. High-IOPS AI NAND is designed for random-access workloads such as vector searches and graph analytics, with Micron targeting configurations delivering approximately 25 million to 100 million IOPS. The company expects products based on this approach to reach the market over the next couple of years.

High-Bandwidth AI NAND is intended to prioritize data throughput. Micron is exploring vertically stacked NAND connected through through-silicon vias and paired with a logic base die, bringing storage closer to AI accelerators. The company says this approach would need to be developed with customers to meet cost and performance requirements.

Micron’s custom-memory plans also include standard and custom HBM4E, followed by custom HBM5E, vertical HBM and vertical Edge Inference Memory. Custom HBM4E could narrow memory I/O or add logic to the base die, freeing space for compute and allowing designs to be tuned for individual AI accelerators.

Micron expects vertical HBM to stack memory directly on CPUs or ASICs rather than placing it beside them on an interposer. The company is considering hybrid bonding, integrated heat spreaders and thermal-aware designs to address packaging and heat challenges. It expects conventional HBM and vertical HBM to coexist in some systems, with the latter serving bandwidth needs and standard HBM providing capacity.

Micron is also collaborating with Meta to optimize LPDDR6 for data-center use, focusing on reliability, serviceability and availability. It expects LPDDR6 to use approximately 35% less power than LPDDR5. The company is developing DDR6 with major customers and says the standard is intended to provide twice the bandwidth of DDR5.

For its DRAM peripheral circuitry, Micron is developing successive CMOS logic technologies, including 3D CMOS. It expects these advances to improve CMOS logic performance by more than tenfold between 2020 and 2030, supporting the bandwidth and power demands of AI-oriented memory products.

Sources: Tom's Hardware.